EP20K60ETC144-3N vs EP20K60EFC144-2XN Comparison
Detailed side-by-side comparison of EP20K60ETC144-3N by Intel and EP20K60EFC144-2XN by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K60ETC144-3N - APEX-20KE FPGA 60K Gates 2560 Logic Elements 144-LQFP | Intel
EP20K60ETC144-3N ObsoleteAltera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndSpecification Comparison
| Parameter | EP20K60ETC144-3N | EP20K60EFC144-2XN |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $152.00 |
| Family | APEX-20KE | APEX-20K (MultiCore Architecture) |
| Typical Gate Count | 60,000 gates | 60,000 gates |
| Logic Elements / Cells | 2,560 | β |
| Embedded Memory (ESB) | 32,768 bits | β |
| Maximum User I/O | 92 | 93 |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.71 V to 1.89 V |
| Internal Frequency | 160 MHz to 182 MHz | β |
| Propagation Delay | 1.72 ns | β |
| Process Technology | 0.22 Β΅m CMOS | β |
| Operating Temperature (Commercial) | 0 Β°C to +85 Β°C | β |
| Package | 144-LQFP (LFQFP, gull-wing, square body) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Series | β | APEX-20KE |
| Logic Elements / Embedded Array Blocks | β | 2,560 |
| Embedded Memory (Bits) | β | 32,768 |
| Number of I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| I/O Supply Voltage (VCCIO) | β | [DATA_NEEDED: VCCIO range] |
| Package Type | β | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | β | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | β | 0 C to +85 C (commercial) |
| Speed Grade | β | -2 (per MPN suffix) |
| Configuration Method | β | JTAG (IEEE 1149.1), Passive Serial, Parallel |