EP2A15B724C7 vs EP2A15B724C Comparison
Detailed side-by-side comparison of EP2A15B724C7 by Altera and EP2A15B724C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A15B724C
EP2A15B724C - APEX II 15K LEs FPGA, 724-BGA | Altera (Intel)
EP2A15B724C ObsoleteSpecification Comparison
| Parameter | EP2A15B724C7 | EP2A15B724C |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $195.00 |
| Family | APEX II | APEX II |
| Manufacturer | Altera (acquired by Intel) | β |
| System Gates | 600,000 | β |
| Logic Elements / Cells | 16,640 | β |
| Total RAM Bits | 425,984 | β |
| Number of I/O | 492 | β |
| Core Voltage | 1.425 V to 1.575 V | β |
| Operating Temperature | 0 C to 85 C (TJ) | [DATA_NEEDED: operating temperature grade] |
| Package | 724-BBGA, FCBGA (35 mm x 35 mm) | 724-Ball FCBGA (FineLine BGA) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Speed Grade | C7 (per part suffix) | C (per suffix; specific speed bin [DATA_NEEDED]) |
| Maximum Internal Frequency | 500 MHz | β |
| Process Technology | 0.15 um all-layer copper | 0.18 micron CMOS |
| LVDS Support | True-LVDS up to 1 Gbps | β |
| Interface Standards | True-LVDS, LVPECL, PCML, HyperTransport | β |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Logic Elements (LEs) | β | 16,640 |
| Maximum User I/O Pins | β | 492 |
| Embedded RAM | β | 425,984 bits |
| Maximum System Gates | β | Up to 1.5M gates (family-level) |
| Embedded System Blocks (ESBs) | β | Configurable as dual-port RAM / ROM / FIFO |
| Interconnect | β | MultiTrack, deterministic |
| I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) |
| PLLs | β | Yes (family-level, up to 4 per device) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| JTAG / Configuration | β | IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) |