EP2A15B724C7 vs EP2A15B724C 比較
詳細並排比較 EP2A15B724C7 由 Altera 與 EP2A15B724C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A15B724C7 | EP2A15B724C |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Manufacturer | Altera (acquired by Intel) | — |
| System Gates | 600,000 | — |
| Logic Elements / Cells | 16,640 | — |
| Total RAM Bits | 425,984 | — |
| Number of I/O | 492 | — |
| Core Voltage | 1.425 V to 1.575 V | — |
| 工作溫度 | 0 C to 85 C (TJ) | [DATA_NEEDED: operating temperature grade] |
| 封裝 | 724-BBGA, FCBGA (35 mm x 35 mm) | 724-Ball FCBGA (FineLine BGA) |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Speed Grade | C7 (per part suffix) | C (per suffix; specific speed bin [DATA_NEEDED]) |
| Maximum Internal Frequency | 500 MHz | — |
| Process Technology | 0.15 um all-layer copper | 0.18 micron CMOS |
| LVDS Support | True-LVDS up to 1 Gbps | — |
| Interface Standards | True-LVDS, LVPECL, PCML, HyperTransport | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance] |
| Logic Elements (LEs) | — | 16,640 |
| Maximum User I/O Pins | — | 492 |
| Embedded RAM | — | 425,984 bits |
| Maximum System Gates | — | Up to 1.5M gates (family-level) |
| Embedded System Blocks (ESBs) | — | Configurable as dual-port RAM / ROM / FIFO |
| Interconnect | — | MultiTrack, deterministic |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) |
| PLLs | — | Yes (family-level, up to 4 per device) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| JTAG / Configuration | — | IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) |