EP2A70F1736C9 vs EP2A70F1736C8 Comparison
Detailed side-by-side comparison of EP2A70F1736C9 by Intel and EP2A70F1736C8 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A70F1736C9 | EP2A70F1736C8 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $105.00 |
| Family | APEX II | — |
| Typical Gates | 70,000 | — |
| Logic Elements | 53,376 (approx) | — |
| Package | 1736-ball FineLine BGA | — |
| Operating Temperature | 0C to +85C (Commercial) | 0°C to 85°C (TJ, commercial) |
| Process Technology | 0.18 um CMOS | 0.18 µm CMOS |
| Core Voltage | 1.5 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Embedded System Blocks (ESBs) | Yes (dual-port RAM/FIFO/CAM capable) | [DATA_NEEDED: ESB count] |
| PLL Count | 4 | [DATA_NEEDED: PLL count] |
| Maximum User I/O Pins | 1072 | — |
| Programming Interface | JTAG (IEEE 1149.1) + in-system | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | APEX II |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements (LEs) | — | 67,200 |
| Total RAM Bits | — | 1,146,880 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (1.5 V nominal) |
| Package / Case | — | 1736-ball FC-BGA |
| Supplier Device Package | — | 1736-pin FC-BGA |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Maximum User I/O | — | [DATA_NEEDED: maximum user I/O count] |
| MultiCore Interconnect | — | Yes (per APEX II family datasheet) |
| Configuration Scheme | — | PS / JTAG / PPA |
| Lead Free | — | Per manufacturer datasheet |
| Moisture Sensitivity Level (MSL) | — | Per JEDEC J-STD-020 (package-dependent) |