EP2AGX190FF35I3G vs EP2AGX190FF35C4G Comparison
Detailed side-by-side comparison of EP2AGX190FF35I3G by Altera and EP2AGX190FF35C4G by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G β Last Time Buy
Specification Comparison
| Parameter | EP2AGX190FF35I3G | EP2AGX190FF35C4G |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,840.00 | $2,350.00 |
| Family | Arria II GX | Arria II GX |
| Logic Elements (LE) | 181,165 | β |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | β |
| User I/O Pins | 612 | β |
| Embedded Memory (bits) | 10,177,536 | 10,177,536 |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | β |
| Transceivers | 8 high-speed transceiver channels (multi-gigabit) | β |
| Embedded Multipliers | [DATA_NEEDED: 18x18 multiplier count] | β |
| PLLs | [DATA_NEEDED: PLL count] | β |
| Core Voltage | 0.9 V | β |
| I/O Voltage Standards | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) | β |
| Process Node | 40 nm | β |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial, suffix I) | β |
| Speed Grade | 3 | C4 |
| Package | 1152-ball FC-FBGA (FF35), 35 mm body | 1152-BBGA, FCBGA (35 mm) |
| Ball Pitch | [DATA_NEEDED: 1.0 mm (typical for FF35)] | β |
| Mounting Type | Surface Mount (flip-chip BGA) | Surface Mount (BGA) |
| RoHS Status | Compliant (suffix G) | Compliant |
| Lead-Free | Yes | Yes |
| Programming Toolchain | Quartus II / Quartus Prime | β |
| Logic Elements | β | 181,165 |
| Equivalent Logic Elements | β | 190,000 |
| Adaptive Logic Modules (ALMs) | β | [DATA_NEEDED: ALM count] |
| Embedded Memory (M20K blocks) | β | [DATA_NEEDED: M20K block count] |
| Embedded 18x18 Multipliers | β | 612 |
| Transceiver Channels | β | 12 (up to 6.375 Gbps) |
| Maximum Transceiver Data Rate | β | 6.375 Gbps |
| Hard PCIe Gen2 Blocks | β | Yes (2) |
| User I/O Pins (maximum) | β | [DATA_NEEDED: user I/O count] |
| Process Technology | β | 40 nm low-power CMOS |
| Operating Temperature Grade | β | Commercial (0C to +85C) |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| Development Tool | β | Quartus II (legacy) |