EP2AGX190FF35I3G vs EP2AGX190FF35C4G Perbandingan
Perbandingan bersamaan detil EP2AGX190FF35I3G dari Altera dan EP2AGX190FF35C4G dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G ⚠ Waktu Beli Terakhir
Perbandingan Spesifikasi
| Parameter Umum | EP2AGX190FF35I3G | EP2AGX190FF35C4G |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Aktif |
| Family | Arria II GX | Arria II GX |
| Logic Elements (LE) | 181,165 | — |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | — |
| User I/O Pins | 612 | — |
| Embedded Memory (bits) | 10,177,536 | 10,177,536 |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Transceivers | 8 high-speed transceiver channels (multi-gigabit) | — |
| Embedded Multipliers | [DATA_NEEDED: 18x18 multiplier count] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Core Voltage | 0.9 V | — |
| I/O Voltage Standards | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) | — |
| Process Node | 40 nm | — |
| Suhu Kerja | -40 °C to +100 °C (industrial, suffix I) | — |
| Speed Grade | 3 | C4 |
| Paket | 1152-ball FC-FBGA (FF35), 35 mm body | 1152-BBGA, FCBGA (35 mm) |
| Ball Pitch | [DATA_NEEDED: 1.0 mm (typical for FF35)] | — |
| Tipe Mounting | Surface Mount (flip-chip BGA) | Surface Mount (BGA) |
| Status RoHS | Compliant (suffix G) | Compliant |
| Lead-Free | Yes | Yes |
| Programming Toolchain | Quartus II / Quartus Prime | — |
| Logic Elements | — | 181,165 |
| Equivalent Logic Elements | — | 190,000 |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory (M20K blocks) | — | [DATA_NEEDED: M20K block count] |
| Embedded 18x18 Multipliers | — | 612 |
| Transceiver Channels | — | 12 (up to 6.375 Gbps) |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Hard PCIe Gen2 Blocks | — | Yes (2) |
| User I/O Pins (maximum) | — | [DATA_NEEDED: user I/O count] |
| Process Technology | — | 40 nm low-power CMOS |
| Operating Temperature Grade | — | Commercial (0C to +85C) |
| Level MSL | — | 3 (per JEDEC J-STD-020) |
| Development Tool | — | Quartus II (legacy) |