EP2S130F1020C5N vs EP2S130F1020C4N Comparison
Detailed side-by-side comparison of EP2S130F1020C5N by Intel and EP2S130F1020C4N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S130F1020C5N | EP2S130F1020C4N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,320.00 | $2,850.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | β |
| Total Memory Bits | 6,747,840 bits | 6,747,840 |
| User I/Os | 734 | β |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | β |
| Maximum Internal Frequency | 609.76 MHz | 711.24 MHz |
| Package | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FC-FBGA |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | Commercial (0C to +85C, C5 grade) | 0C to +85C (commercial, inferred from C grade) |
| Temperature Grade | C5 (other - per Partstack) | β |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| PLLs | 4 (typical Stratix II feature) | β |
| Global Clock Networks | 16 (typical Stratix II feature) | β |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | JTAG / Passive Serial / Active Serial |
| Country of Origin | Republic of Korea (per GlobalSpec) | β |
| ECCN | 3A001.a.7.a (per GlobalSpec) | β |
| Estimated EOL Date | 2023 (per GlobalSpec) | β |
| Logic Array Blocks (LABs) | β | 6,627 |
| Maximum User I/O | β | 742 |
| Core Voltage (VCCINT) | β | 1.2 V |
| Speed Grade | β | C4 (commercial) |
| MSL Level | β | 3 (per JEDEC J-STD-020, typical for FC-BGA) |
| Design Tool | β | Quartus II (legacy, up to v13.0sp1) |