EP2S130F1020C5N vs EP2S130F1020C4N 对比
详细并排对比 EP2S130F1020C5N 出自 Intel 和 EP2S130F1020C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2S130F1020C5N | EP2S130F1020C4N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,320.00 | $2,850.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | — |
| Total Memory Bits | 6,747,840 bits | 6,747,840 |
| User I/Os | 734 | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | 711.24 MHz |
| 封装 | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FC-FBGA |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| 工作温度 | Commercial (0C to +85C, C5 grade) | 0C to +85C (commercial, inferred from C grade) |
| Temperature Grade | C5 (other - per Partstack) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| PLLs | 4 (typical Stratix II feature) | — |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | JTAG / Passive Serial / Active Serial |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Logic Array Blocks (LABs) | — | 6,627 |
| Maximum User I/O | — | 742 |
| Core Voltage (VCCINT) | — | 1.2 V |
| Speed Grade | — | C4 (commercial) |
| MSL 等级 | — | 3 (per JEDEC J-STD-020, typical for FC-BGA) |
| Design Tool | — | Quartus II (legacy, up to v13.0sp1) |