EP2S30F672I4 vs EP2S60F67214N Comparison
Detailed side-by-side comparison of EP2S30F672I4 by Intel and EP2S60F67214N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S30F672I4 | EP2S60F67214N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $695.00 | $232.00 |
| Series | Stratix II | β |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | 33880 | 60,440 LE |
| Logic Array Blocks (LABs) | 1694 | β |
| Total RAM Bits | 1369728 | 2,544,192 bit (2.5 Mbit) |
| Number of I/O | 500 | β |
| DSP Blocks | 12 (per datasheet, family range) | 12 |
| Number of PLLs | 6 | β |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | β |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| Package / Case | 672-BBGA, FCBGA (FBGA-672) | β |
| Package Dimensions | 35 x 35 mm | β |
| Ball Pitch | 1.0 mm | β |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | SRAM-based, configured via bitstream |
| MSL Level | 3 (per JEDEC J-STD-020) | 3 (168 hours floor life) |
| RoHS Status | [DATA_NEEDED: confirm RoHS compliance on part label] | Lead-free / RoHS compliant |
| Family | β | Stratix II |
| Phase-Locked Loops (PLLs) | β | 4 |
| Package | β | 672-ball FBGA (FineLine BGA) |
| Speed Grade | β | I4 (industrial, fast) |
| Core Voltage | β | 1.2 V (typical) |
| I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O count for FBGA-672] |