EP2S30F672I4 vs EP2S60F67214N Vergleich
Detaillierter Direktvergleich von EP2S30F672I4 von Intel und EP2S60F67214N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S30F672I4 | EP2S60F67214N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $695,00 | $232,00 |
| Series | Stratix II | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33880 | 60,440 LE |
| Logic Array Blocks (LABs) | 1694 | — |
| Total RAM Bits | 1369728 | 2,544,192 bit (2.5 Mbit) |
| Number of I/O | 500 | — |
| DSP Blocks | 12 (per datasheet, family range) | 12 |
| Number of PLLs | 6 | — |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Betriebstemperatur | -40C to +100C (Industrial) | -40C to +100C (industrial) |
| Montageart | Surface Mount | Surface Mount |
| Gehäuse / Bauform | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | SRAM-based, configured via bitstream |
| MSL-Level | 3 (per JEDEC J-STD-020) | 3 (168 hours floor life) |
| RoHS-Status | [DATA_NEEDED: confirm RoHS compliance on part label] | Lead-free / RoHS compliant |
| Family | — | Stratix II |
| Phase-Locked Loops (PLLs) | — | 4 |
| Gehäuse | — | 672-ball FBGA (FineLine BGA) |
| Speed Grade | — | I4 (industrial, fast) |
| Core Voltage | — | 1.2 V (typical) |
| I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count for FBGA-672] |