EP3SE110F1152C4L vs EP3SE110F1152C3N Comparison
Detailed side-by-side comparison of EP3SE110F1152C4L by Intel and EP3SE110F1152C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE110F1152C3N - Stratix III E FPGA, 107.5K LE, FC-FBGA-1152 | Intel
EP3SE110F1152C3N β Last Time BuySpecification Comparison
| Parameter | EP3SE110F1152C4L | EP3SE110F1152C3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,372.13 | $1,560.00 |
| Device Type | FPGA - Field Programmable Gate Array | β |
| Series | Stratix III E | Stratix III |
| Logic Elements | 107500 | β |
| Embedded Memory | 8936448 bits (8.9 Mbit) | β |
| Maximum User I/O | 744 | β |
| Internal Frequency | 800 MHz (max) | β |
| Core Supply Voltage | 0.9 V | 1.1 V nominal |
| Package | 1152-ball FCBGA (BBGA-1152) | β |
| Package Type | FBGA (Fine-pitch BGA) | FC-FBGA-1152 (flip-chip BGA) |
| Pins | 1152 | β |
| Speed Grade | C4 (speed grade 4) | C3 |
| Operating Temperature | 0C to 85C (commercial) | 0 Β°C to 85 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Manufacturer | Intel (formerly Altera) | β |
| Family | β | Stratix III E |
| Logic Elements (LE) | β | 107,500 |
| Logic Array Blocks (LABs) | β | 4,300 |
| Total RAM Bits | β | 8,936,448 |
| User I/Os | β | 744 |
| Operating Frequency (max) | β | 500 MHz |
| I/O Supply Voltage | β | [DATA_NEEDED: I/O supply range] |
| Process Technology | β | 65 nm TSMC |
| Mounting Style | β | SMD/SMT (Tray) |
| DSP Blocks | β | Yes (embedded multipliers) |
| Memory Type | β | M9K and M144K block RAM |
| External Memory Support | β | DDR/DDR2/DDR3 with read/write leveling |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |
| RoHS | β | [DATA_NEEDED: RoHS status] |
| Lead-Free | β | Yes (per Altera/Intel datasheet family convention) |