EP610DC-10 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActiveSpecification Comparison
| Parameter | EP610DC-10 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through-Hole | Through Hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS EPROM (UV-erasable) |
| Supply Voltage | 5 V (single supply) | — |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | — |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |