EP610DC-10 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610DC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $10.40 |
| Device Family | Altera Classic EPLD | β |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | β |
| Speed Grade | -10 | -30 (30 ns tPD) |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CERDIP (windowed) |
| Mounting Type | Through-Hole | Through-Hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS EPROM |
| Supply Voltage | 5 V (single supply) | β |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0C to +70C) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 (with output enable) |
| Logic Elements | 16 macrocells (programmable AND/OR array) | β |
| Configuration Memory | UV-erasable EPROM | β |
| Reprogrammable | Yes (UV erase window on package) | β |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Family | β | EP610 (Classic Device Family) |
| Logic Expanders | β | 4 (4 product terms per macrocell) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 30 ns |
| Dedicated Inputs | β | 16 |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |