EP610DC-10 vs EP610DC-30 Vergleich
Detaillierter Direktvergleich von EP610DC-10 von Intel und EP610DC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DC-10 | EP610DC-30 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $10,40 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | -30 (30 ns tPD) |
| Gehäuse | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CERDIP (windowed) |
| Montageart | Through-Hole | Through-Hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS EPROM |
| Versorgungsspannung | 5 V (single supply) | — |
| Betriebstemperatur | 0C to +70C (commercial) | Commercial (0C to +70C) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 (with output enable) |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS-Status | [DATA_NEEDED: not stated in verified web data] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Dedicated Inputs | — | 16 |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |