EP610DC-10 vs EP610DC15 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DC15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610DC15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole | Through-Hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS |
| Supply Voltage | 5 V (single supply) | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | — |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | unknown |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 Classic EPLD |
| Architecture | — | PAL-type |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |