EP610DC-15 vs EP610ILC-25 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610ILC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-15 | EP610ILC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | 0C to 70C (commercial) | — |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 28-pin PLCC (J-lead) |
| Mounting Type | Through-Hole | Surface Mount |
| Programming Method | JEDEC fuse map, UV erasure | In-system, electrically erasable |
| Technology | CMOS | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610 series) |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Operating Temperature Range | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |