EP610DC-15 vs EP610ILC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-15 sa pamamagitan ng Altera at EP610ILC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-15 | EP610ILC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperature na Operasyon | 0C to 70C (commercial) | — |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 28-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount |
| Programming Method | JEDEC fuse map, UV erasure | In-system, electrically erasable |
| Technology | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610 series) |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Hanay ng Temperature na Operasyon | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |