EP610DC-25 vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β Active
Specification Comparison
| Parameter | EP610DC-25 | EP610DI-25 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.95 |
| Family | Altera Classic EPLD | β |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | β |
| Maximum Propagation Delay (tPD) | 25 ns | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Number of I/O Pins | 22 | β |
| Number of Dedicated Inputs | 4 | β |
| Total Pin Count | 24 | β |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | β |
| Mounting Type | Through Hole | Through-Hole (DIP) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Operating Temperature | 0 C to +70 C | Industrial (per "I" suffix) |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable) |
| Programming Method | JEDEC fuse-map / UV-erase | β |
| Speed Grade Suffix | -25 (25 ns tPD) | 25 = 25 ns |
| Part Family | β | Classic EPLD |
| Propagation Delay (tPD) | β | 25 ns |
| Maximum Pipelined Clock Frequency | β | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | β | 16 (bidirectional) |
| Dedicated Inputs | β | 4 |
| Total User I/O | β | 20 |
| Package Type | β | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin Count | β | 24 |
| Compliance | β | RoHS status unknown (legacy 1990s part) |