EP610DC-25 vs EP610DI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-25 sa pamamagitan ng Rochester Electronics at EP610DI-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | EP610DC-25 | EP610DI-25 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | Altera Classic EPLD | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Packhaging | 24-pin CDIP (Ceramic DIP, through-hole) | — |
| Uri ng Pagpapasok | Through Hole | Through-Hole (DIP) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Temperature na Operasyon | 0 C to +70 C | Industrial (per "I" suffix) |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable) |
| Programming Method | JEDEC fuse-map / UV-erase | — |
| Speed Grade Suffix | -25 (25 ns tPD) | 25 = 25 ns |
| Part Family | — | Classic EPLD |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | — | 16 (bidirectional) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Bilang ng Pin | — | 24 |
| Compliance | — | RoHS status unknown (legacy 1990s part) |