EP610DC-30 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-30 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| Package | 24-pin CERDIP (windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Operating Temperature | Commercial (0C to +70C) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Device Type | — | CPLD - Classic EPLD |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |
| RoHS Status | — | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |