EP610DC-30 vs EP610DC-35 तुलना
विस्तृत दोनों ओर की तुलना EP610DC-30 द्वारा Altera और EP610DC-35 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP610DC-30 | EP610DC-35 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| पैकेज | 24-pin CERDIP (windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| माउंटिंग प्रकार | Through-Hole | Through-Hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| ऑपरेटिंग तापमान | Commercial (0C to +70C) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Device Type | — | CPLD - Classic EPLD |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |
| RoHS स्थिति | — | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |