EP610DC15 vs EP610DC-20 Comparison
Detailed side-by-side comparison of EP610DC15 by Intel and EP610DC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC15 | EP610DC-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.50 | $15.85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | EP610 Classic EPLD | Classic EP610 |
| Macrocells | 16 | β |
| Architecture | PAL-type | β |
| Propagation Delay (tPD) | 15 ns | 22 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Total Inputs | 20 | β |
| I/O Lines | 16 | β |
| Product Terms | 160 | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS | β |
| Operating Temperature | 0C to +70C | 0 Β°C to 70 Β°C (commercial) |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Through-Hole | Through-hole |
| Reprogrammability | Yes (UV erasable via windowed package) | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| Logic Macrocells | β | 16 |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 16 (bidirectional) |
| Total Usable Pins | β | 20 |
| Product Terms (p-terms) | β | 160 |
| Maximum Toggle Frequency (fMAX) | β | 55.6 MHz |
| Programming Method | β | UV erasure + parallel programmer |
| Process Technology | β | CMOS, UV-erasable floating gate |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |