EP610DC15 vs EP610DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC15 sa pamamagitan ng Intel at EP610DC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC15 | EP610DC-20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | EP610 Classic EPLD | Classic EP610 |
| Macrocells | 16 | — |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | 22 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Total Inputs | 20 | — |
| I/O Lines | 16 | — |
| Product Terms | 160 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS | — |
| Temperature na Operasyon | 0C to +70C | 0 °C to 70 °C (commercial) |
| Packhaging | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Uri ng Pagpapasok | Through-Hole | Through-hole |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |