EP610DI-25 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610DI-25 by Intel and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-25 | EP610DC-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS, EPROM-based (UV-erasable) |
| Supply Voltage (VCC) | 5 V nominal | — |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Pin Count | 24 | — |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Operating Temperature | Industrial (per "I" suffix) | 0C to +70C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Package | — | 24-pin CDIP (Ceramic DIP, windowed) |
| Supply Voltage | — | 5 V (single supply) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS Status | — | [DATA_NEEDED: not stated in verified web data] |