EP610DI-25 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DI-25 by Intel and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-25 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | — |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Pin Count | 24 | — |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| Operating Temperature | Industrial (per "I" suffix) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Device Type | — | CPLD - Classic EPLD |
| Family | — | Altera Classic EP610 |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Package | — | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |
| RoHS Status | — | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |