EP610DI-25 vs EP610DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DI-25 sa pamamagitan ng Intel at EP610DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DI-25 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | — |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Bilang ng Pin | 24 | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Temperature na Operasyon | Industrial (per "I" suffix) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Device Type | — | CPLD - Classic EPLD |
| Family | — | Altera Classic EP610 |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Packhaging | — | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |
| Tindminan RoHS | — | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |