EP610DI-30N vs EP610IDC-15 Comparison
Detailed side-by-side comparison of EP610DI-30N by Altera and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-30N | EP610IDC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | 66 MHz |
| Supply Voltage (VCC) | 5 V ±5% | 4.75 V to 5.25 V (5 V nominal) |
| Package | CDIP-24 (Ceramic DIP, windowed) | 24-pin CerDIP (ceramic DIP) |
| Pin Count | 24 | — |
| Operating Temperature | -40°C to +85°C (industrial) | 0C to +70C (commercial) |
| Process Technology | CMOS | CMOS, UV-erasable / OTP |
| Programming Method | UV-erasable (windowed ceramic) | — |
| Mounting Type | Through-hole (DIP) | Through-hole |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |