EP610IDC-15 vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-15 | EP610DI-25 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 25 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Operating Temperature | 0C to +70C (commercial) | Industrial (per "I" suffix) |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Package | 24-pin CerDIP (ceramic DIP) | — |
| Mounting Type | Through-hole | Through-Hole (DIP) |
| I/O Pins | 24 (per package; macrocell-programmable) | 16 (bidirectional) |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | [DATA_NEEDED: RoHS status of CerDIP variant] | — |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Part Family | — | Classic EPLD |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin Count | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |