EP610ILC-25 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-25 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $7.95 |
| Family | Classic EPLD (EP610 series) | β |
| Device Type | EEPLD (Electrically Erasable PLD) | β |
| Usable Gates | 300 | β |
| Macrocells | 16 | 16 |
| Product Terms | 160 | β |
| Maximum Operating Frequency (fMAX) | 40 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | β |
| Total Inputs | 20 | β |
| Dedicated Inputs | 4 | 20 |
| Bidirectional I/O Pins | 16 | 16 |
| Operating Temperature Range | 0 C to +70 C (commercial) | β |
| Package | 28-pin PLCC (J-lead) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | β |
| Programming Method | In-system, electrically erasable | JEDEC fuse map, UV erasure |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Logic Expanders | β | 4 |
| Total Product Terms | β | 160 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Operating Temperature | β | 0C to 70C (commercial) |
| Technology | β | CMOS |