EP610ILC-25 vs EP610DC-15 比較
詳細な並列比較: EP610ILC-25 メーカー: Altera および EP610DC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610ILC-25 | EP610DC-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $7.95 |
| Family | Classic EPLD (EP610 series) | — |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 20 |
| Bidirectional I/O Pins | 16 | 16 |
| 動作温度範囲 | 0 C to +70 C (commercial) | — |
| パッケージ | 28-pin PLCC (J-lead) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 実装タイプ | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | JEDEC fuse map, UV erasure |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Total Product Terms | — | 160 |
| Propagation Delay (tPD) | — | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| 動作温度 | — | 0C to 70C (commercial) |
| Technology | — | CMOS |