EP610ILC-25 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610ILC-25 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $9.95 |
| Family | Classic EPLD (EP610 series) | Altera Classic EPLD |
| Device Type | EEPLD (Electrically Erasable PLD) | β |
| Usable Gates | 300 | β |
| Macrocells | 16 | 16 |
| Product Terms | 160 | β |
| Maximum Operating Frequency (fMAX) | 40 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Nominal Supply Voltage | 5 V | β |
| Total Inputs | 20 | β |
| Dedicated Inputs | 4 | β |
| Bidirectional I/O Pins | 16 | β |
| Operating Temperature Range | 0 C to +70 C (commercial) | β |
| Package | 28-pin PLCC (J-lead) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Surface Mount | Through Hole |
| Process Technology | CMOS, electrically erasable | β |
| Programming Method | In-system, electrically erasable | JEDEC fuse-map / UV-erase |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Operating Temperature | β | 0 C to +70 C |
| Technology | β | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | β | -25 (25 ns tPD) |