EP610ILC-25 vs EP610DC-25 对比
详细并排对比 EP610ILC-25 出自 Altera 和 EP610DC-25 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 量产中规格对比
| 参数 | EP610ILC-25 | EP610DC-25 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.85 | $9.95 |
| Family | Classic EPLD (EP610 series) | Altera Classic EPLD |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| 工作温度范围 | 0 C to +70 C (commercial) | — |
| 封装 | 28-pin PLCC (J-lead) | 24-pin CDIP (Ceramic DIP, through-hole) |
| 安装类型 | Surface Mount | Through Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | JEDEC fuse-map / UV-erase |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| 工作温度 | — | 0 C to +70 C |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |