EP610ILC-25 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-25 | EP610DC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | EP610 (Classic Device Family) |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 16 |
| Bidirectional I/O Pins | 16 | — |
| Operating Temperature Range | 0 C to +70 C (commercial) | — |
| Package | 28-pin PLCC (J-lead) | 24-pin CERDIP (windowed) |
| Mounting Type | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |
| Operating Temperature | — | Commercial (0C to +70C) |