EP610ILC-25 vs EP610DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-25 sa pamamagitan ng Altera at EP610DC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC-25 | EP610DC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | EP610 (Classic Device Family) |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 16 |
| Bidirectional I/O Pins | 16 | — |
| Hanay ng Temperature na Operasyon | 0 C to +70 C (commercial) | — |
| Packhaging | 28-pin PLCC (J-lead) | 24-pin CERDIP (windowed) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |
| Temperature na Operasyon | — | Commercial (0C to +70C) |