EP610LC-15 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610LC-15 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-15 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.65 | $7.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EPLD (EP610) | β |
| Logic Elements / Macrocells | 16 macrocells | β |
| Equivalent Gates | 300 gates | β |
| Propagation Delay (tpd) | 15 ns | β |
| Counter Frequency (fmax) | 83.3 MHz | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (Vcc) | 5 V (single supply) | β |
| Process Technology | CMOS | β |
| Package | 28-pin PLCC (J-lead, plastic OTP) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Surface Mount | Through-Hole |
| Number of Pins | 28 | β |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0C to 70C (commercial) |
| Programming | OTP (one-time programmable) | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Macrocells | β | 16 |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Programming Method | β | JEDEC fuse map, UV erasure |
| Technology | β | CMOS |