EP610LC-15 vs EP610DC-15 对比
详细并排对比 EP610LC-15 出自 Altera 和 EP610DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610LC-15 | EP610DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.65 | $7.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP610) | — |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| 封装 | 28-pin PLCC (J-lead, plastic OTP) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 安装类型 | Surface Mount | Through-Hole |
| 引脚数 | 28 | — |
| 工作温度 | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0C to 70C (commercial) |
| Programming | OTP (one-time programmable) | — |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS status] |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Propagation Delay (tPD) | — | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Method | — | JEDEC fuse map, UV erasure |
| Technology | — | CMOS |