EP610LC-30 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610LC-30 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $9.95 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable) |
| Package | 24-pin CERDIP / PDIP | 24-pin CDIP (Ceramic DIP, through-hole) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 C to +70 C |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Through Hole |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Programming Method | β | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | β | -25 (25 ns tPD) |