EP610LC-30 vs EP610DC-25 Comparação
Comparação detalhada lado a lado de EP610LC-30 por Intel e EP610DC-25 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ AtivoComparação de especificações
| Parâmetro | EP610LC-30 | EP610DC-25 |
|---|---|---|
| Marca | Intel | Rochester Electronics |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $16,40 | $9,95 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable) |
| Encapsulamento | 24-pin CERDIP / PDIP | 24-pin CDIP (Ceramic DIP, through-hole) |
| Temperatura de operação | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 C to +70 C |
| Erase/Program Cycles | 1000 typical | — |
| Tipo de montagem | Through-Hole | Through Hole |
| Tipo de saída | CMOS tri-state (programmable) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |