EP610LC-35 vs EP610LC-25 Comparison
Detailed side-by-side comparison of EP610LC-35 by Altera and EP610LC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-35 | EP610LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Series | EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS |
| Package | 28-pin PLCC (J-lead) | PLCC-28 |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0C to +70C (commercial) |
| Speed Grade | -35 (slowest EP610) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| MSL Level | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Supply Voltage | — | 5 V ±5% |
| Programmability | — | UV-erasable (windowed package) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |