EP610PC-15 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610PC-15 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610PC-15 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $9.95 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Usable Gates | 300 gates | β |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | β |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | β |
| TTL Emulation | 100% TTL compatible | β |
| Package | PDIP-24 (plastic DIP, 24-pin) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Pin Count | 24 pins | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C |
| Mounting Type | Through-Hole (DIP) | Through Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Development Tool | Altera MAX+PLUS II | β |
| Logic Test Circuitry | On-board for AC/DC verification | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Programming Method | β | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | β | -25 (25 ns tPD) |