EP610PC-15 vs EP610DC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-15 sa pamamagitan ng Altera at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Rochester Electronics
EP610DC-25 EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

EP610DC-25 ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EP610PC-15 EP610DC-25
Brand Altera Rochester Electronics
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Aktibo
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 300 gates —
Macrocells 16 16
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Maximum Counter Frequency 100 MHz (per family datasheet) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS CMOS EPROM (UV-erasable)
Architecture PAL-type, sum-of-products AND/OR array —
TTL Emulation 100% TTL compatible —
Packhaging PDIP-24 (plastic DIP, 24-pin) 24-pin CDIP (Ceramic DIP, through-hole)
Bilang ng Pin 24 pins —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0 C to +70 C
Uri ng Pagpapasok Through-Hole (DIP) Through Hole
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Development Tool Altera MAX+PLUS II —
Logic Test Circuitry On-board for AC/DC verification —
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

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