EP610PC-20 vs EP610PC-20T Comparison
Detailed side-by-side comparison of EP610PC-20 by Altera and EP610PC-20T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20 | EP610PC-20T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V |
| Number of Pins | 24 | — |
| Package | PDIP-24 | 24-pin PDIP (Plastic DIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS Status | Non-compliant (legacy PDIP) | unknown |
| Logic Elements / Macrocells | — | 16 macrocells |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Mounting Type | — | Through-Hole |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |