EP610PC-20 vs EP610PC-20T 比較
詳細並排比較 EP610PC-20 由 Altera 與 EP610PC-20T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-20 | EP610PC-20T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V |
| 腳位數 | 24 | — |
| 封裝 | PDIP-24 | 24-pin PDIP (Plastic DIP) |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS 狀態 | Non-compliant (legacy PDIP) | unknown |
| Logic Elements / Macrocells | — | 16 macrocells |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| 安裝類型 | — | Through-Hole |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |