EP610PC-20T vs EP610IPC-10 Comparison
Detailed side-by-side comparison of EP610PC-20T by Intel and EP610IPC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20T | EP610IPC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | — |
| Propagation Delay (tPD) | 20 ns | 15 ns (commerical -10 grade) |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Mounting Type | Through-Hole | — |
| Operating Temperature | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | unknown | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Macrocells | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Product Terms | — | 160 total |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| Total Input Pins | — | 20 |
| Supply Voltage | — | 5 V |
| Architecture | — | Turbo-only AND-OR-NOT, PAL-type |
| Technology | — | CMOS EPROM (UV-erasable / OTP) |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |