EP610PC-20T vs EP610IPC-10 比較
詳細並排比較 EP610PC-20T 由 Intel 與 EP610IPC-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-20T | EP610IPC-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | — |
| Propagation Delay (tPD) | 20 ns | 15 ns (commerical -10 grade) |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| 封裝 | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| 安裝類型 | Through-Hole | — |
| 工作溫度 | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | unknown | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Macrocells | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Product Terms | — | 160 total |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| Total Input Pins | — | 20 |
| 供應電壓 | — | 5 V |
| Architecture | — | Turbo-only AND-OR-NOT, PAL-type |
| Technology | — | CMOS EPROM (UV-erasable / OTP) |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |