EP610PC-20T vs EP610IPC-25 Comparison
Detailed side-by-side comparison of EP610PC-20T by Intel and EP610IPC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20T | EP610IPC-25 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | Classic EPLD | Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Mounting Type | Through-Hole | Through-Hole |
| Operating Temperature | 0C to +70C (Commercial) | 0 °C to +70 °C (Commercial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | unknown | Non-compliant (contains Pb, PDIP package) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |