EP610PC-20T vs EP610IPC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-20T sa pamamagitan ng Intel at EP610IPC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610PC-20T | EP610IPC-25 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Classic EPLD | Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Packhaging | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0 °C to +70 °C (Commercial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| Tindminan RoHS | unknown | Non-compliant (contains Pb, PDIP package) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |