EP610PC-20T vs EP610PC-15 Comparison
Detailed side-by-side comparison of EP610PC-20T by Intel and EP610PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20T | EP610PC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | 300 gates |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Package | 24-pin PDIP (Plastic DIP) | PDIP-24 (plastic DIP, 24-pin) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | Altera MAX+PLUS II |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Pin Count | — | 24 pins |
| Logic Test Circuitry | — | On-board for AC/DC verification |