EP610PC-20T vs EP610PC-15 Comparación
Comparación detallada lado a lado de EP610PC-20T por Intel y EP610PC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610PC-20T | EP610PC-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,20 | $17,50 |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | 300 gates |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Encapsulado | 24-pin PDIP (Plastic DIP) | PDIP-24 (plastic DIP, 24-pin) |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | Altera MAX+PLUS II |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Recuento de pines | — | 24 pins |
| Logic Test Circuitry | — | On-board for AC/DC verification |