EP910DC-30 vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-30 | EP910DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $10.75 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | β |
| Gate Count | 900 usable gates | β |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Clock Frequency (fCNT) | 33.3 MHz | β |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | β |
| External Clock Pins | 2 (CLK1, CLK2) | β |
| Supply Voltage | 5 V | β |
| Process Technology | CMOS | β |
| Programming Method | UV-Erasable / OTP | β |
| Package | DIP-40 (through-hole, 600 mil) | 24-pin ceramic DIP (DC) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Mounting Type | Through-Hole | Through-Hole |
| Device Density | β | 900 usable gates |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | β | 12 |
| Flip-Flops | β | 10 |
| Product Terms per Macrocells | β | 24 |
| Maximum Propagation Delay (tPD) | β | 15 ns |
| Speed Grade | β | 15 |
| Supply Voltage (VCC) | β | 5 V (typical) |
| Technology | β | CMOS EPROM, UV-erasable |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| RoHS Status | β | [DATA_NEEDED: not explicitly stated in verified data] |